Timeplan (and Tools lower down)
 

My time plan v1.0, due to a lot of change and updates probably.

Week 1-4

Reading about OSE, how it works and especially how interrupts are handled. Writting small applications to better understand OSE. Reading about PowerPC and getting familiar with it's instruction set and how to manipulate the cache. Setting up and installing a environment in which I can work in, meening getting familiar with the tools and hardware I'll be using.

Week 5-6

Rewrite the code that runs after an interrupt from C-code to assembler and start analyzing what happens in the cache. Also look at overlapping, since the PowerPC has "only" 2-way associative cache can I place the interrupt procedure so that it doesn't affect other procedures that much? (probably not, I can't control were the compiler places the code, but some compilers can recompile code after profiling it, can that improve performance?)

Week 7-8

To be solved: What part of the code should be locked into the cache. How do I find out where in the memory the code lies that I want to lock. How do I make efficient use of the cache, since a cache block is four words long, how do I make efficient use of an entire block? How do I measure performace after locking, I've already thought a little about that and I think I'll use the simulator to get the hitrate in the cache and then run on hardware to measure actuall interrupt latency and total system time.

Week 9-12

Code the locking, when finished start to measure performance.Try various configurations when it comes to how much of the code should be locked and also what part of the code should be locked. I hope to have preliminary results at the end of week 10. If I have a positive result then perhaps I should get in touch with companies using OSE if they are willing to try running there applications using my cache optimized interrupt handeling.

Week 13-14

Finding out what other setups (ie processors, MIPS, ARM, etc) that OSE runs on  have support for cache optimizations. Also looking into the source code for the kernel of OSE to learn more about it's functionallity. Can I identify the longest run where interrupts are disabled and if so is it necessary to disable interrupts for that part of the code? Can interrupts be enabled in the code afterall and if so will it improve performance.

Week 15-17

Start summerizing up the thesis project, there will probably be some stuff that I havn't have time to do. Also if the results are positive talk to the developers on if and how it can be included in future versions of OSE, probably as a feature in OSE. Then it will probably require some sort of official documentation which I must write.

Week 18-20

Write the major part of the actual thesis project. Probably do some complemneting measurements, maybe write a specific program.
 

Tools
 

Hardware

Host platform:  Standard desktop x86-PC running NT 4.0
Target platform: PowerPC MBX board

Software

OSE 4.2, Enea OSE Systems - RTOS which I'll be working on.
SingelStep, Software Development Systems Inc. - For running and debugging both in simulator and target platform.
Diab Compiler, Software Development Systems Inc. - Compiling for PowerPC target.
GCC, GNU - another compiler for PowerPC and SoftKernel targets.
Multi 2000, GreenHill - Compiling and debugging PowerPC code.
Visual C++, MicroSoft - compiling for the SoftKernel OSE version.
XEmacs, GNU - my editor of choice.